Location: Bangalore
Eligibility:
Masters in Engineering/ Bachelors in Engineering from a reputed institute with good academic record
0 to 1+ years of experience and should have executed P & R
Job profile:
• Participate in all the different phases of Physical design implementation of SoCs.
• Participate in Block level Physical design of complex Chip/IPs.
• Participate in STA and Timing Closure activities
• Work with chip integration team closely in Timing closure
How to apply:
For more details and apply click HERE
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