Job Opening For Verification Engineer In nSys Design Systems @ Delhi

Experience:0 – 2 Years
Job Title:Verification Engineer
Location: Delhi/NCR
Education:UG – B.Tech, B.E. – Computers, Electrical, Electronics,Telecommunication, Instrumentation, PG – M.Tech – Computers, Electronics,Telecommunication, Instrumentation
Compensation:Rupees 3,00,000 – 6,00,000,A great start with excellent growth prospects

Job Description:
Verification of Emerging Protocols, SOC
Coding of Designs / Behavioral Models
Desired Profile:
Sound Digital Design Fundamentals is essential
Knowledge of microprocessors is essential
Knowledge of Verilog/System Verilogis preferred
Excellent communication skills
Excellent academics
Company Profile:
nSys is a privately funded company, managed by professionals highly experienced in the area of leading edge technologies. nSys leverages the world’s largest portfolio of Verification IPs it has developed, to provide products & services to Accelerate Designs of its customers developing ASIC, FPGA or IP.
Contact Details:
Executive Name:Shilpa
Email Address:hr@nsysinc.com
Reference ID:nSys_VE